AC coupling circuit having a large capacitance and a good frequency response

ABSTRACT

This invention is directed to reduce degradation, loss, and reflection of high frequency signals of a coupling circuit for an alternating current. The coupling circuit, for connecting a first circuit element to a second circuit element, comprises a die capacitor and a chip capacitor connected in parallel to each other. The die capacitor has a first electrode that faces to and is in contact with the first circuit element, and a second electrode that is wire-bonded to the second circuit element. The chip capacitor also has a first electrode that is in contact with the first circuit element and a second electrode that is in contact with the second electrode of the die capacitor. The coupling circuit may show both advantages of superior performance at high frequencies attributed to the die-capacitor and relative large capacitance attributed to the chip-capacitor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present relates to an alternating current (AC) circuit, especially,relates to an AC circuit in which a capacitor is used for electricallyconnecting circuit elements.

2. Related Prior Art

An AC circuit operating in a high frequency band uses specific circuitelements such as transmission line types of a micro-strip and aco-planar, and a passive element with a chip shape. In order toelectrically connect active elements, such as an amplifier, the ACcoupling circuit must be set between them because direct current (DC)levels of these active elements are different to each other. Forexample, in the case that two amplifier are serially connected, theoutput DC level of the precedent amplifier often mismatches to the inputDC level of the succeeding one. The AC coupling circuit generallyincludes a coupling capacitor set on the transmission line connectingthe preceding circuit to the succeeding one.

FIG. 1 shows a conventional arrangement of the coupling capacitor. InFIG. 1, an integrated circuit 11 with a bare chip shape is connected, bya plural bonding wires 24 a to 24 c, to a wiring substrate 11 on whichtwo ground patterns 22 a and 22 b sandwich a transmission line 21therebetween. The transmission line 21 is split and the capacitor 23 ismounted on the line 21 so as to connect the split line.

In such AC coupling circuit shown in FIG. 1, even in the case that thetransmission line 21 and the ground patterns adjacent thereto is sodesigned to adjust the transmission impedance, an impedance mismatchingmay occur at points the coupling capacitor is connected to thetransmission line. This causes a reflection, loss and deterioration ofthe signal transmitted thereon.

Further, a gap between the substrate 11 and the IC 12 must be secured atleast 200 μm, which causes bonding wires 24 a to 24 c longer than 400 μmor amount to 500 μm. Such long and slim bonding wire behaves as aninductor. For example, a ribbon wire with a 50 μm in width and a 20 μmin thickness has a parasitic inductance of about 200 pH. The parasiticinductance inherently accompanied with the bonding wire degrades qualityof high frequency signals by the resonance with input capacitance of theIC 12.

SUMMARY OF THE INVENTION

One aspect of the present invention is to provide a coupling circuitthat keeps the quality of the transmitted high frequency signal, andreduces a loss and a reflection of the signal.

According to one aspect of the present invention, a coupling circuit,for connecting a first circuit element to a second circuit elementcomprises a die capacitor and a chip capacitor. The die capacitor has afirst electrode that faces to and is in contact with the first circuitelement, and a second electrode that is wire-bonded to the secondcircuit element. The chip capacitor also has a first electrode that isin contact with the first circuit element and a second electrode that isin contact with the second electrode of the die capacitor.

Since the die capacitor and the chip capacitor, thus arranged, areconnected in parallel, the coupling circuit may show each advantage.Namely, the die capacitor has a parallel-plate-like structure withsuperior performance at high frequencies. On the other hand, the chipcapacitor has comb-shaped electrodes that enables to widen an area ofthe electrode and to bring electrodes close to each other, therebyincreasing the capacitance of the chip capacitor.

In the present invention, one of circuit elements may be a co-planarline and the other of circuit elements may be a co-planar line or anintegrated circuit.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a conventional arrangement of a coupling capacitor;

FIG. 2A is a plan view showing an arrangement of coupling capacitorsaccording to the first embodiment of the present invention, and FIG. 2Bis a side view of the arrangement of the first embodiment;

FIG. 3 is an equivalent circuit diagram of the first embodiment;

FIG. 4 is a reflection spectrum of a conventional coupling circuit, andFIG. 4B is a reflection spectrum of the present coupling circuit;

FIG. 5A is a plan view showing the second embodiment of the presentinvention, and FIG. 5B is a side view of the second embodiment;

FIG. 6A is a plan view showing the third embodiment of the presentinvention and FIG. 6B is a side view of the third embodiment;

FIG. 7 is an arrangement showing the fourth embodiment of the presentinvention;

FIG. 8 is an arrangement showing the fifth embodiment of the presentinvention; and

FIG. 9A is a plan view showing a sixth embodiment of the presentinvention, and FIG. 9B is a circuit diagram of the sixth embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

Next, preferred embodiments of the present invention will be describedas referring to accompanying drawings.

FIG. 2 shows an arrangement of a coupling capacitor according to thepresent invention. FIG. 2A is a plan view of a substrate made ofceramics that is encased in a metal package, and FIG. 2B is a side view.The ceramic substrate 31 provides a coplanar line thereon, whichincludes a signal line 41 and a pair of ground patters 42 a and 42 bsandwiching the signal line 41. The signal line 41 is split into twoportions 41 a and 41 b. On an edge of the signal line 41 a, a diecapacitor 44 is mounted such that a one surface of the die capacitor 44faces to the signal line 41 a. Another surface of the die capacitor 44is electrically connected to an edge of anther signal line 41 b with abonding wire made of gold (Au). Further, a chip capacitor 43 isconnected between another surface of the die capacitor 44 and the signalline 41 a such that the one electrode of the chip-capacitor 43 isdirectly soldered to another surface of the die capacitor. Thus, thesignal line split into two lines and two capacitors, one is the diecapacitor 44 and the other is the chip capacitor 43 constitutes thecoupling circuit.

As shown in FIG. 2, the die capacitor 44 is a capacitor having aparallel-plate type of electrodes sandwiching a dielectric materialtherebetween. An upper surface corresponds to one electrode while thebottom surface thereof is another electrode. Generally, the capacitanceof the die capacitor is small relative to that of the chip capacitor.The die capacitor is directly mounted on the signal line 31 such thatthe bottom surface thereof is in contact with the signal line 41 a. Onthe other hand, the upper electrode is wire-bonded to anther signal line41 b.

The chip capacitor 43 is a capacitor having comb-like electrodes.Between teethes of one electrodes is inter-digitally inserted teethes ofanother electrodes, thereby widening the equivalent area of theelectrodes. The chip capacitor shows a greater capacitance relative tothe die capacitor. However, due to its comb-like structure, the chipcapacitor shows an inferior high frequency performance to the diecapacitor. Namely, the chip capacitor has a greater parasitic inductancethan the die capacitor.

FIG. 3 is an equivalent circuit diagram of the coupling circuit. A chipcapacitor 43 having a greater capacitance and a die capacitor 44 havingrelatively smaller capacitance are connected in parallel to the splitsignal line 41 a and 41 b. The chip capacitor 43 exhibits a desiredperformance at relatively low frequencies, while the die capacitor 44exhibits a performance at high frequencies. Therefore, by inserting twocapacitors each connected in parallel and showing different performance,the coupling circuit applicable to wide frequency range may be obtained.

The co-planar line 41 preferably has the same width as that of the chipcapacitor 43. When the width of both elements are same, an impedancemismatching at the connecting point between the co-planar line 41 andthe chip capacitor 43 may be reduced. One example of such arrangement isthat, in FIG. 2, the chip capacitor is a 0603 type having 600 μm inlength and 300 μm in width, the width of the co-planar line 41 is 300μm, and gaps between the co-planar line 41 and adjacent ground patterns42 is 200 μm, The dimension of the die capacitor 44 is 380 μm square.When the size of the die capacitor 44 is equal to the width of theco-planar line 41, the impedance mismatching may be further reduced,

FIG. 4 is reflection characteristics of coupling circuit. The reflectioncharacteristic is evaluated by the parameter of S11. Namely, Closer thevalue of the S11 to 0 dB, the greater the reflection, which the signaltransmitted in the co-planar line is influenced by the impedancemismatching. FIG. 4A corresponds to the conventional coupling circuit,while FIG. 4B reflects the present circuit. In the present couplingcircuit shown in FIG. 4B, the frequency responses can be improved below30 GHz.

FIG. 5 is a second coupling circuit according to the present invention.FIG. 5A is a plan view showing a ceramic substrate 31 enclosed in ametal package 33 and an IC chip 32 in a bare chip shape. FIG. 5B is aside view of the second coupling circuit. On the ceramic substrate 31, aco-planar line 41 with predetermined gaps between adjacent groundpatterns 42 a and 42 b is provided. At an edge of the co-planar line 41,one electrode of the die capacitor 44 is connected, while the otherelectrode of the die capacitor is wire-bonded to the bare chip IC 32with a gold wire 45 a.

Between the co-planar line 41 and the other terminal of the diecapacitor 44, a chip capacitor is arranged, thus two capacitorsconstitute the coupling circuit. In a coupling circuit that connects theIC to the co-planar line, a point between the co-planar line and thecapacitors and another point between the one electrode of the diecapacitor 44 and the bonding wire may cause an impedance mismatching.Therefore, the IC 32 in FIG. 5 is directly bonded to upper electrode ofthe die capacitor 44, which reduces the points where the impedancemismatching may occur.

FIG. 6 is still another embodiment of the present invention. FIG. 6Ashows two ceramic substrates 31 a and 31 b both enclosed in a metalpackage 33, and an IC in the bare chip shape. In FIG. 6A, only thebottom of the metal package 33 is appeared. On the ceramic substrate 31a, a co-planar line 41 is provided. The co-planar line 41 is formed suchthat gaps in both side thereof between respective ground patterns 42 aand 42 b are formed. At an edge of the co-planar line 41, one electrodeof the die capacitor 44 is connected, while the upper electrode thereofis connected to the bare chip IC with a bonding wire 45 a. The chipcapacitor 43 is assembled such that one electrode thereof is directlyfacing to the co-planar line 41, and the other electrode is directlyconnected to the upper electrode of the die capacitor 44, thusconstituting the coupling circuit.

The die capacitor 44 is assembled on the co-planar line 41 such that theedge of the die capacitor 44 is sticking out from the edge of theco-planar line 41 toward the bare chip IC 32. The gap between the IC 32and the co-planar line is typically 200 μm due to the assembly of the IC32. However, the present embodiment enables to narrow the gapstherebetween, thereby shortening the bonding wire 45 a. Thus, thearrangement of the present embodiment can reduce the parasiticinductance of the bonding wire 45 a, the deterioration and the loss ofthe signal at high frequencies.

Between the ceramic substrate 31 a and the bare chip IC 32, an insulatedresin 46 is preferably filled under the die capacitor 44 to reinforcethe die capacitor when the wire 45 a is bonded thereto.

FIG. 7 shows a third example of the present invention. The thirdcoupling circuit comprises a ceramic substrate 31 and a bare chip IC 32both enclosed in a metal package 33. FIG. 7 shows only the bottom plateof the metal package 33. The die capacitor 44 is assembled at the edgeof the co-planar line 41, and the other electrode of the die capacitor44 is bonded to the IC 32 with a bonding wire 45. Similar to theprevious example, the chip capacitor 43 is assembled such that oneelectrode thereof is directly connected to the co-planar line 41 and theother electrode is directly soldered to the upper electrode of the diecapacitor 44, thus the co-planar line and two capacitors constitute thecoupling circuit.

According to FIG. 7, the die capacitor 44 is mounted such that the edgethereof is sticking out from the edge of the co-planar line 41 with theinsulated resin inserted between the substrate 31 and the bare chip IC32, and is tilting toward the IC 32. When the level of the upper surfaceof the IC 32 and that of the substrate 31 is different, the arrangementshown in FIG. 7 enables to place the IC 32 close enough to the substrate31.

FIG. 8 is a plan view showing a fourth embodiment of the presentinvention. The coupling circuit shown in FIG. 8 comprises a ceramicsubstrate 31 and the bare chip IC 32. On the ceramic substrate 31, aco-planar line, which has a signal line 41 and a pair of ground patterns42 a and 42 b sandwiching the signal line therebetween, is formed. Thedie capacitor 44 is arranged at the edge of the signal line with oneelectrode thereof facing to the signal line 41, while the other terminalof the die capacitor 44 is wire-bonded to the bare chip IC 32. The edgeof the die capacitor 44 is sticking out from the edge of the substrate31 toward the IC 32. The chip-capacitor 43 is assembled such that theone electrode thereof directly soldered to the signal line 41 and theother electrode is soldered to the upper electrode of the die capacitor44. Thus, two capacitors 43 and 44, and the co-planar line 41 constitutea coupling circuit.

As described with referring to FIG. 2, discontinuity points inmechanical and electrical along the signal transmission line may causethe impedance mismatching. To reduce this impedance mismatching, theembodiment shown in FIG. 8 provide a pair of metal block 47 a and 47 b,each mounted on the edge of the ground pattern 42 a and 42 b. Thetransmission characteristic of the co-planar line 41, such astransmission impedance, is determined by a thickness and the dielectricconstant of the substrate 31, thickness of the signal line 41 and theground patters 42 a and 42 b, these types of metal, and the gaps betweenthe signal line 41 and the ground patterns 42 a and 42 b. Thearrangement shown in FIG. 9 enables to adjust the gaps at the edge ofthe signal line, the impedance mismatching is further improved.

FIG. 9 is a fifth embodiment of the present invention. FIG. 9A is a planview of the coupling circuit that comprises a ceramic substrate 31 and abare chip IC 32 enclosed in a metal package. FIG. 9B is an equivalentcircuit diagram of the coupling circuit shown in FIG. 9A. A co-planarline having a signal line 41 and a pair of ground patterns 42 a and 42 bsandwiching the signal line 41 with a predetermined gap are formed onthe substrate 31. On the edge of the signal line 41, a die capacitor 44is assembled such that one electrode thereof is facing to the signalline 41. Another electrode of the die capacitor 44 is wire-bonded to thebare chip IC 32. The edge of the die capacitor 44 is sticking out fromthe edge of the substrate 31. The chip capacitor 43 is assembled suchthat the one electrode thereof is connected to the signal line 41, whilethe other electrode thereof is soldered to the upper electrode of thedie capacitor 44. Thus, two capacitors 43 and 44 constitute the couplingcircuit.

On the upper electrode of the die capacitor 44, an inductor 48 isconnected. In FIG. 9, a relatively long and slim bonding wire 48functions as the inductor. Another terminal of the inductor 48 issupplied a power supply to operate the IC 32 from outside of thepackage. Such configuration shown in FIG. 9 is called as a bias-T, whichenables to provide a bias to the output terminal of the IC 32. Accordingto the present arrangement, the bias-T may be realized with fewer pointswhere the impedance mismatching may occur.

1. A coupling circuit for connecting a co-planar line provided on aceramic substrate to an integrated circuit in a bare chip shape, saidcoupling circuit comprising: a die capacitor connecting said co-planarline to said integrated circuit, said die capacitor having a firstelectrode facing to and being in contact with said co-planar line and asecond electrode wire-bonded to said integrated circuit; and a chipcapacitor connecting said co-planar line to said integrated circuit,said chip capacitor having a first electrode in direct contact with saidco-planar line and a second electrode in direct contact with said secondelectrode of said die capacitor, wherein said die capacitor is mountedin an end portion of said co-planar line such that an edge of said diecapacitor sticks out from an edge of said co-planar line.
 2. Thecoupling circuit according to claim 1, wherein said substrate isenclosed in a metal package with said integrated circuit.
 3. Thecoupling circuit according to claim 1, further includes an insulatingresin filled under said die capacitor.
 4. The coupling circuit accordingto claim 1, wherein said die-capacitor is tilting toward said integratedcircuit.
 5. The coupling circuit according to claim 1, further includingan inductor connected to said second electrode of said die capacitor,wherein said coupling circuit and said inductor comprises a bias-Tcircuit.
 6. The coupling circuit according to claim 4, further includingan insulating resin filled under said die capacitor.